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Modeling of the Effects of Process Variations on Circuit Delay at 65nm

TitleModeling of the Effects of Process Variations on Circuit Delay at 65nm
Publication TypeConference Paper
Year of Publication2005
AuthorsHarish, BP, Patil, MB, Bhat, N
Conference Name2005 IEEE Conference on Electron Devices and Solid-State Circuits
Date PublishedDec
Keywordsanalytical modeling, Analytical models, Circuit simulation, Computational modeling, delay distribution, Delay effects, Digital circuits, Fluctuations, Implants, Integrated circuit technology, mixed-mode simulations, Monte Carlo analysis, Monte Carlo methods, process variations, Software libraries

A novel methodology for modeling the effects of process variations on circuit delay performance is proposed by relating the variations in process parameters to variations in delay metric of a complex digital circuit. The delay of a 2-input NAND gate with 65nm gate length transistors is extensively characterized by mixed-mode simulations which is then used as a library element. The variation in saturation current Ionat the device level, and the variation in rising/falling edge stage delay for the NAND gate at the circuit level, are taken as performance metrics. A 4-bit x 4-bit Wallace tree multiplier circuit is used as a representative combinational circuit to demonstrate the proposed methodology. The variation in the multiplier delay is characterized, to obtain delay distributions, by an extensive Monte Carlo analysis. An analytical model based on CV/I metric is proposed, to extend this methodology for a generic technology library with a variety of library elements.