| Title | Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs |
| Publication Type | Conference Paper |
| Year of Publication | 2007 |
| Authors | Harish, BP, Bhat, N, Patil, MB |
| Conference Name | Computing: Theory and Applications, 2007. ICCTA '07. International Conference on |
| Date Published | March |
| Keywords | 65 nm, Circuit simulation, CMOS design, CMOS digital integrated circuits, CMOS process, Design methodology, design of experiments, digital circuit, Digital circuits, dynamic power dissipation, hybrid model., integrated circuit design, integrated circuit modelling, least mean squares methods, least squares method, logic gates, mixed-mode simulations, Monte Carlo analysis, Monte Carlo methods, multiplier circuit, NAND gate library, Power dissipation, process variability-aware statistical hybrid modeling, response surface methodology, Semiconductor device modeling, Software libraries, US Department of Energy |
| Abstract | A generalized technique is proposed for modeling the effects of process variations on dynamic power by directly relating the variations in process parameters to variations in dynamic power of a digital circuit. The dynamic power of a 2-input NAND gate is characterized by mixed-mode simulations, to be used as a library element for 65nm gate length technology. The proposed methodology is demonstrated with a multiplier circuit built using the NAND gate library, by characterizing its dynamic power through Monte Carlo analysis. The statistical technique of response surface methodology (RSM) using design of experiments (DOE) and least squares method (LSM), are employed to generate a "hybrid model" for gate power to account for simultaneous variations in multiple process parameters. We demonstrate that our hybrid model based statistical design approach results in considerable savings in the power budget of low power CMOS designs with an error of less than 1%, with significant reductions in uncertainty by at least 6X on a normalized basis, against worst case design |
| DOI | 10.1109/ICCTA.2007.108 |
