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Role of thermal annealing on SiGe thin films fabricated by PECVD

TitleRole of thermal annealing on SiGe thin films fabricated by PECVD
Publication TypeJournal Article
Year of Publication2015
AuthorsJoseph, S, Saraf, N, Umamaheswara, A, Madakasira, V, Bhat, N
JournalMaterials Science in Semiconductor Processing
Keywordsgrain size, Hardness, PECVD, SiGe thin film, Strain relaxation, Thermal annealing

Amorphous Silicon Germanium (a-SiGe) thin films of 500 nm thickness are deposited on silicon substrates using Plasma Enhanced Chemical Vapour Deposition (PECVD). To obtain polycrystalline nature of films, thermal annealing is done at various temperature (450–600 °C) and time (1–10 h). The surface morphology of the pre- and post-annealed films is investigated using scanning electron microscopy (SEM) and atomic force microscopy (AFM). The crystallographic structure of the film is obtained by X-ray diffraction method. Raman spectroscopy is carried out to quantify the Ge concentration and the degree of strain relaxation in the film. Nano-indentation is performed to obtain the mechanical properties of the film. It is found that annealing reduces the surface roughness of the film and increases the Ge concentration in the film. The grain size of the film increases with increase in annealing temperature. The grain size is found to decrease with increase in annealing time up to 5 h and then increased. The results show that 550 °C for 5 h is the critical annealing condition for variation of structural and mechanical properties of the film. Recrystallization starts at this condition and results in finer grains. An increase in hardness value of 7–8 GPa has been observed. Grain growth occurs above this critical annealing condition and degrades the mechanical properties of the film. The strain in the film is only relaxed to about 55% even for 10 h of annealing at 600 °C. Transmission Electron Microscopy (TEM) observations show that the strain relaxation occurs by forming misfit dislocations and these dislocations are confined to the SiGe/Si interface.