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Publications

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A. S. Medury, Majumdar, K. , Bhat, N. , and Bhat, K. N. , Modeling the threshold voltage of ultra-thin-body(UTB) long channel symmetric double-gate (DG) MOSFETs, in Semiconductor Device Research Symposium, 2009. ISDRS '09. International, 2009, pp. 1-2.
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K. Majumdar, Konjady, R. S. , Suryaprakash, R. T. , and Bhat, N. , Underlap Optimization in HFinFET in Presence of Interface Traps, IEEE Transactions on Nanotechnology, vol. 10, pp. 1249-1253, 2011.