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Publications

Found 15 results
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Filters: Keyword is logic gates  [Clear All Filters]
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B
R. Baby, Reshma, K. , Chandrasekar, H. , Muralidharan, R. , Raghavan, S. , and Nath, D. N. , “Study of TaN-gated p-GaN E-mode HEMT”, IEEE Transactions on Electron Devices, vol. 70, pp. 1607–1612, 2023.
S. Bhattacharjee, Ganapathi, K. Lakshmi, Sharma, D. Ganesh, Sharma, A. , Mohan, S. , and Bhat, N. , “Adaptive Transport in High Performance (I on), Steep Sub-Threshold Slope (SS< 60 mV/dec) MoS 2 Transistors”, IEEE Transactions on Nanotechnology, vol. 18, pp. 1071–1078, 2019.
D
S. Dana and Varma, M. M. , “Gas-Selective Signal Amplification in Fluctuation-Based Graphene FET Sensors”, IEEE Sensors Journal, vol. 16, pp. 6533–6536, 2016.
S. Dana and Varma, M. M. , “Gas-Selective Signal Amplification in Fluctuation-Based Graphene FET Sensors”, IEEE Sensors Journal, vol. 16, pp. 6533-6536, 2016.
G
K. Lakshmi Ganapathi, Bhattacharjee, S. , Mohan, S. , and Bhat, N. , “High-performance HfO 2 back gated multilayer MoS 2 transistors”, IEEE Electron Device Letters, vol. 37, pp. 797–800, 2016.
K. L. Ganapathi, Bhattacharjee, S. , Mohan, S. , and Bhat, N. , “High-Performance HfO2 Back Gated Multilayer MoS2 Transistors”, IEEE Electron Device Letters, vol. 37, pp. 797-800, 2016.
K. L. Ganapathi, Bhat, N. , and Mohan, S. , “Optimization of oxygen flow rate for e-beam evaporated HfO2 thin films”, in Emerging Electronics (ICEE), 2012 International Conference on, 2012, pp. 1-4.
P. R. Yasasvi Gangavarapu, Lokesh, P. C. , Bhat, K. N. , and Naik, A. K. , “Graphene Electrodes as Barrier-Free Contacts for Carbon Nanotube Field-Effect Transistors”, IEEE Transactions on Electron Devices, vol. 64, pp. 4335–4339, 2017.
S. Dutta Gupta, Soni, A. , Joshi, V. , Kumar, J. , Sengupta, R. , Khand, H. , Shankar, B. , Mohan, N. , Raghavan, S. , Bhat, N. , and , , “Positive Threshold Voltage Shift in AlGaN/GaN HEMTs and E-Mode Operation By $${$$\backslash$mathrm ${$Al$}$$}$ _ ${$x$}$${$$\backslash$mathrm ${$Ti$}$$}$ _ ${$1-x$}$ $ O Based Gate Stack Engineering”, IEEE Transactions on Electron Devices, vol. 66, pp. 2544–2550, 2019.
H
B. P. Harish, Bhat, N. , and Patil, M. B. , “Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs”, in Computing: Theory and Applications, 2007. ICCTA '07. International Conference on, 2007, pp. 94-98.
T. H. Hung, Park, P. S. , Krishnamoorthy, S. , Nath, D. N. , Bajaj, S. , and Rajan, S. , “Lateral energy band engineering of Al2O3/III-nitride interfaces”, in 72nd Device Research Conference, 2014, pp. 131-132.
K
S. Kumar, Gupta, P. , Guiney, I. , Humphreys, C. J. , Raghavan, S. , Muralidharan, R. , and Nath, D. N. , “Temperature and Bias Dependent Trap Capture Cross Section in AlGaN/GaN HEMT on 6-in Silicon With Carbon-Doped Buffer”, IEEE Transactions on Electron Devices, vol. 64, pp. 4868–4874, 2017.
M
K. Majumdar, Konjady, R. S. , Suryaprakash, R. T. , and Bhat, N. , “Underlap Optimization in HFinFET in Presence of Interface Traps”, IEEE Transactions on Nanotechnology, vol. 10, pp. 1249-1253, 2011.
P
P. S. Park, Nath, D. N. , and Rajan, S. , “Quantum Capacitance in N-Polar GaN/AlGaN/GaN Heterostructures”, IEEE Electron Device Letters, vol. 33, pp. 991-993, 2012.
Y
J. Yang, Cui, S. , Ma, T. P. , Hung, T. H. , Nath, D. N. , Krishnamoorthy, S. , and Rajan, S. , “Determination of trap energy levels in AlGaN/GaN HEMT”, in Device Research Conference (DRC), 2013 71st Annual, 2013, pp. 79-80.