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Publications

Found 2 results
Author Title [ Type(Desc)] Year
Filters: Keyword is Delay effects  [Clear All Filters]
Conference Paper
B. P. Harish, Patil, M. B. , and Bhat, N. , Modeling of the Effects of Process Variations on Circuit Delay at 65nm, in 2005 IEEE Conference on Electron Devices and Solid-State Circuits, 2005, pp. 761-764.
Journal Article
B. P. Harish, Bhat, N. , and Patil, M. B. , On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, pp. 606-614, 2007.