B. P. Harish, Bhat, N. , and Patil, M. B. ,
“On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology”,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, pp. 606-614, 2007.
B. P. Harish, Bhat, N. , and Patil, M. B. ,
“On A Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance”,
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 26, pp. 606–614, 2007.
]