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DTSTART;TZID=Asia/Kolkata:20260923T160000
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SUMMARY:[Seminar] : Engineering Dielectric Interfaces in Nanoscale Transistors
DESCRIPTION:Speaker: Prof. Dipanjan Sen\, Postdoctoral Associate\, Research Laboratory of Electronics (RLE)\, Massachusetts Institute of Technology (MIT).\n\nTitle: "Engineering Dielectric Interfaces in Nanoscale Transistors"\n\nDate: Wednesday\, 23rd September 2026 - Time: 4 PM\n\nHi-Tea & Coffee: 5 PM\n\nVenue: CeNSE Seminar Hall\n\nAbstract:\n\nAs scaling enters the Ångström era\, the frontier is shifting from the semiconductor channel toward \nthe dielectric and its interfaces. In atomically thin systems\, channel-dielectric coupling becomes \nstrong enough to define device behavior. This talk shows how that coupling in 2D heterostructures \nenables cryogenic non-volatile ferroelectric memory\, programmable threshold-voltage engineering for \nlow-power 2D CMOS\, solid-state iontronic thermometry\, and neuromorphic photon–ion–electron-coupled devices. \nExtending the same philosophy to mainstream CMOS scaling\, ultrathin ALD-grown HfO2–ZrO2 gate stacks \nengineered near the atomic limit enhance gate capacitance and scale equivalent oxide thickness beyond \nconventional interfacial-layer limits\, while preserving transport\, leakage\, and reliability. \nDielectrics thus emerge as active materials\, motivating a forward-looking program on atomically \nengineered gate stacks for CMOS and beyond-CMOS devices.\n\nBiography:\n\nDipanjan Sen is a Postdoctoral Associate in the Research Laboratory of Electronics (RLE) at \nthe Massachusetts Institute of Technology\, where he works with Prof. Suraj Cheema on gate-stack \nengineering for CMOS and beyond CMOS devices. His current research focuses on extreme EOT scaling \nthrough ultrathin\, ALD-grown gate stacks and their integration into foundry-relevant platforms. \nHe earned his PhD at the Pennsylvania State University in the group of Prof. Saptarshi Das\, where \nhis work on 2D-material/dielectric interfaces produced a broad family of emerging devices spanning \ncryogenic ferroelectric memory\, threshold-voltage engineering for 2D CMOS\, iontronic sensing\, and \nneuromorphic computing\, with results appearing in journals including Nature Electronics\, Nature \nCommunications\, Nature Sensors\, ACS nano etc. Across his work\, Dipanjan is driven by a single \nquestion- how the engineering of dielectric interfaces\, atom by atom\, can unlock new functionality \nand extend the limits of the modern transistor.\n\nHost Faculty:  Prof. Manoj Varma
URL:https://www.cense.iisc.ac.in/event/seminar-engineering-dielectric-interfaces-in-nanoscale-transistors/
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