CORE FACULTY

Navakanta Bhat

Navakanta Bhat

Professor

Room No: SF 05
Email: navakant@iisc.ac.in; navakant@gmail.com
Phone: +91 80 22933312
FAX: +91 80 23606475
Group Webpage: Nano Devices and Sensors Lab Associated
Departments: Department of Electrical Communication Engineering

Education
• Ph.D. EE, 1996, Stanford University, Stanford, CA, USA.
• MTech. Microelectronics, 1992, Indian Institute of Technology, Bombay, India.
• B.E. Electronics & Communication, 1989, SJCE University of Mysore, India.

Experience
• Professor, Indian Institute of Science, Bangalore, India, Dec. 2010 – Current.
• Associate Professor, Indian Institute of Science, Bangalore, India, Jan. 2005 – Dec. 2010.
• Assistant Professor, Indian Institute of Science, Bangalore, India, Oct. 1999 – Jan 2005.
• Device Engineer, Advanced Products R&D Lab, Motorola, Austin, TX, USA, Jan. 1997-July 1999.

Research Interests
• Nanoelectronics device physics and technology
• Electrochemical Biosensors
• Metal oxide gas sensors
• Novel materials and processes for CMOS and MEMS applications

Research Area
Electrochemical Biosensors, SERS & Lab-on-a-chip devices, Gas sensors, 2D nanoelectronics with MoS2 and Graphene, Al/GaN high electron mobility transistors, novel materials and processes for CMOS & MEMS applications

Recent Publications

  • Kumari, N., Vaishnav, M. S., Srikanta, S., Krishnaswamy, P. R., & Bhat, N. (2024). Exploring glycated sites in human serum albumin: Impact of sample processing techniques on detection and analysis. Analytical Methods16(30), 5239-5247.
    https://doi.org/10.1039/D4AY00503A
  • Vaishnav, M. S., Kumari, N., Srikanta, S., Simha, V., Krishnaswamy, P. R., Balaram, P., & Bhat, N. (2024). Albumin Oxidation and Albumin Glycation Discordance During Type 2 Diabetes Therapy: Biological and Clinical Implications. Metabolic Syndrome and Related Disorders.
    https://doi.org/10.1089/met.2023.0275
  • Khandelwal, U., Sandilya, R. S., Rai, R. K., Sharma, D., Mahapatra, S. R., Mondal, D., Bhat N., Avasthi, S., Chandorkar.S.A. & Nukala, P. (2024). Large electro-opto-mechanical coupling in VO2 neuristors. Applied Physics Reviews11(2).
    https://doi.org/10.1063/5.0169859

Key Publications

  • Das, S., Sebastian, A., Pop, E., McClellan, C. J., Franklin, A. D., Grasser, T., … & Singh, R. (2021). Transistors based on two-dimensional materials for future integrated circuits. Nature Electronics4(11), 786-799.
    https://www.nature.com/articles/s41928-021-00670-1

      Patents
      • N. Bhat, K N Bhat, V T Arun, “Modification of Fermi-level pinning behaviour at the Germanium surface through sulfur passivation treatment” , Indian Patent filed.

      • B. Amrutur, N. Bhat, “Large Flexible Surfaces with an Embedded, Dense, Sensing and Actuation Network for Bio-Electronic applications” Indian and US Patent filed.

      • B. Amrutur, N. Bhat, S. Dwivedi, “Adaptive Digital Baseband Receiver” , Indian Patent Filed, 2596/CHE/2009 , October 2009.

      • N. Bhat, Balaji Jayaraman, S.A.Shivashankar, Rudra Pratap, “A sub-threshold Cap-FETsensor for sensing analyte, a method and system thereof” Indian Patent Application Number: 906/CHE/2007, International PCT Application Number: PCT/IN2008/000385.

      • N. Bhat, Thejas, Rudra Pratap, “A sub-threshold Forced plate-FET sensor for sensing inertial displacements, a method and system thereof”, Indian Patent Application Number: 907/CHE/2007.

      • International PCT Application Number: PCT/IN2008/000386.

      • N. Bhat, C. Malhi, Rudra Pratap, “A sub-threshold Elastic deflection-FET sensor for sensing pressure/force, a method and system thereof”, Indian Patent Application Number: 929/CHE/2007, International PCT Application Number: PCT/IN2008/000387.

      • N. Bhat and Rakesh Gnana David J., “An adaptive keeper circuit to control domino logic dynamic circuits using rate sensing technique”, Patent filed, International application PCT/IN2007/000259, Indian Patent No.01130/CHE/2007.

      • N. Bhat and S. Mukherjee, “Yield and Speed Enhancement of Semiconductor Integrated Circuits using Post Fabrication Transistor Mismatch Compensation Circuitry”, US patent #6934200.

      • P. Tsui, H. Tseng, N. Bhat and P. Chen, “Method for making a dual thickness gate oxide layer using a nitride/oxide composite region”, US patent #5960289.

      • P. Chen, N. Bhat, D. Pham, P. Tsui, “Process for forming semiconductor device with thick and thin films,” US Patent #6,261,978.