Students

Education • B.E., ECE, (2010), Government Engineering College, Idukki, Kerala, India. • M.Tech., VLSI- Design, (2014), Vellore Institute of Technology (VIT), Vellore, Tamil Nadu, India. Experience • Project Associate, CeNSE, IISc, Bangalore, India, (Aug 2015 – Jul 2016). • Research Assistant, IIT Bombay, Mumbai, India, (Jul 2014 – Jul 2015). • Electronics Engineer, A S Moloobhoy & Sons, Mumbai, India, (Sep 2010 – Oct 2011). Publications • S. Dev, Nayana Remesh, Y. Rawal, P. P. Manik, B. Wood, and S. Lodha, “Low resistivity contact on n-type Ge using low work-function Yb with a thin TiO2 interfacial layer”, Applied Physics Letters, 108 (10), 103507 (2016). • Nayana Remesh, Reena Monica “DESIGN OF LOW POWER BAUGH WOOLEY MULTIPLIER USING CNTFET”, (Published in IASTER’s International Journal of Research in Electronics & Communication Engineering, Volume 1, Issue 2, October-December, 2013) Conference and Seminars • P. P. Manik, S. Dev, Nayana Remesh, Y. Rawal, S. Khopkar, S. Lodha, “Ge n-channel FinFET Performance Enhancement Using Low Work Function Metal-Interfacial Layer-Ge Contacts” accepted at VLSI-TSA, Hsinchu, Taiwan, April 2017. • Nayana Remesh, S. Dev, Y. Rawal, s. Khopkar, P. P. Manik, B. Wood, A. Brand, S. Lodha, “Contact barrier height and resistivity reduction using low work-function metal (Yb)-interfacial layer-semiconductor contacts on n-type Si and Ge” DRC 2015.