B.Tech. Electronics and Communication, MG University, Kerala.
M.E. VLSI Design, Anna University, Tamil Nadu.
Experience:
Lecturer, Cochin University of Science And Technology(CUSAT), Kerala, October 2006 - March 2007.
Lecturer, Viswajyothi College of Engineering and Technology (VJCET), Kerala, August 2009 - July 2010.
Theses Title (Year):
ASIC Implementation of a High Throughput, Low Latency, Memory Optimized FFT Processor. (2016)
Publications
Kala S, Nalesh S, S K Nandy and Ranjani Narayan, ‘Scalable and Energy Efficient, Dynamically Reconfigurable FFT Architecture”, Journal of Low Power Electronics,Vol. 11, No.3, September 2015.
