Applications are invited from eligible Indian Nationals for the position of Project Technical Staffs to work in a MeitY-funded project at CeNSE, IISc, under the supervision of Prof. Sreetosh Goswami. The position involves hands-on clean room fabrication, process-flow optimization, and device development based on molecular electronics.

Project Description

About 75% of today’s enterprise-generated data is created and processed outside traditional data centres and cloud infrastructure. This shift has given rise to edge computing, where computational tasks are performed near sensor/detector networks within the Internet of Things. Molecular electronics offers a transformative pathway for such applications because molecular systems are flexible, wearable, highly scalable, and capable of delivering ultra-low-energy devices with energy efficiency far superior to conventional inorganic technologies. Transition metal complexes of redox-active ligands are of particular interest, acting as stable electron sponges and offering up to six non-volatile electronic states depending on applied bias. Recent studies have shown that azo-aromatic ligand complexes outperform state-of-the-art inorganic memristors in stability, endurance, robustness, and both energy and space efficiency. The experimental work in this project begins with synthesizing tailor-made metal complexes and evaluating their resistive memory behaviour through thin-film and nanodevice fabrication. Both metal ions and ligands can be tuned to achieve desirable electronic properties. At CeNSE, IISc, we have already demonstrated cutting-edge neuromorphic molecular devices that significantly outperform traditional systems such as Intel Haswell CPUs and NVIDIA GPUs in speed, resolution, and space efficiency [Ref. 1–10]. Given that the global market size for Artificial Intelligence (AI) is projected between USD 3.5 to 5.8 trillion, capturing a share of this market can substantially shape the country’s technological and economic trajectory. This MeitY-sponsored project (3 years) aims to develop one of the world’s most energy-efficient AI/ML accelerators on CMOS, with strong potential for technology incubation and start-up development at IISc after project completion.

Position Details

Role Title: Project Technical Staff – Clean Room Fabrication & Process Optimization

Nature of Appointment: Project-based / Contractual

Work Location: CeNSE, Indian Institute of Science (IISc)

Reporting To: Prof. Sreetosh Goswami (PI)

Key Responsibilities

• Perform clean room fabrication processes such as lithography, thin-film deposition, etching, CMP, and device patterning
• Develop, test, and optimize fabrication process flows and recipes for molecular electronic devices
• Conduct repeated trials and refine parameters to achieve improved device yield and performance
• Maintain detailed logs of fabrication parameters, results, and characterisation data
• Prepare device samples, operate critical fabrication tools, and assist in troubleshooting
• Work closely with the PI and project team on experiment planning, data recording, and report preparation

Required Qualifications

• M.Sc. or M. Tech in: Physics / Chemistry / Materials Science
• B. Tech or M. Tech in: Electronics / Electrical Engineering Related Fields
• Prior experience with clean room tools or micro/nanofabrication (desirable but not mandatory)
• Strong technical aptitude, willingness to learn fabrication processes, and interest in hands-on experimental work

Remuneration / Fellowship

· Based on qualification and experience, as per project norms

How to Apply Eligible candidates may send their CV to moncs.recruitment@gmail.com with the subject line: “Application for Project Technical Staff”

The deadline for application is 25th March 2026.

References

[1] S, H., Bhat, N. & Goswami, S. Nat Electron 8, 752–756 (2025).

[2] D. Sharma, Rath, S.P., Kundu, B. … N. Bhat … S. Goswami. Nature, 2024

[3] S. Goswami, et.al. Nature materials 2017, 16, 1216.

[4] S. Goswami, et.al., Nature nanotechnology 2020, 15, 380.

[5] S. Goswami, et.al., Nature 2021, 597, 51.

[6] S. P. Rath, D. Thompson, S. Goswami, S. Goswami, Advanced Materials, 2204551.

[7] S.P. Rath, D. Sharma, N. Bhat, S. Goswami, & S. Goswami, Advanced Materials, 2022, 2206128.

[8] https://iisc.ac.in/events/building-energy-efficient-computing-platforms/

[9] https://timesofindia.indiatimes.com/home/science/iisc-building-new-energy-efficient-computing-platforms/articleshow/95939493.cms

[10] https://www.deccanherald.com/technology/iisc-scientists-report-computing-breakthrough-3187052

I-STEM National AI Systems Internship (12–20 Weeks)

Building India’s AI-Driven Scientific Instrument & Research Intelligence Engine

India has invested billions in research infrastructure.
The next leap is not procurement.
It is intelligence.

At I-STEM, we are initiating a national-level AI Systems Engineering Internship to build what I believe
is a foundational layer for India’s future research ecosystem:

An AI-Driven Scientific Instrument & Research Intelligence System
This is not a chatbot internship.
This is not a basic ML project.

This is a structured deep-technology initiative to architect a multi-layer AI system that can:
• Recommend appropriate scientific instruments
• Guide intelligent sample preparation
• Optimize experimental parameters
• Assist in result interpretation
• Progress toward secure offline LLM deployment inside laboratory infrastructure

We are building research intelligence — not interfaces.

Why This Matters

Across institutions, researchers struggle not because instruments are absent, but because scientific  decision intelligence is fragmented.
Instrument manuals are static.
SOPs are generic.
Parameter selection is experience-dependent.
Interpretation is uneven.

We aim to change that.

This internship contributes to the foundation of India’s AI-enabled research infrastructure  architecture.

Project Architecture
Selected interns will work on designing a three-layer AI reasoning framework.

A. Intelligent Equipment Recommendation Engine
(Scientific Decision Intelligence Layer)
Objective: Build an AI system capable of structured scientific reasoning — beyond keyword  matching.

The system must:
Accept structured research intent:
• Research objective
• Sample type
• Domain
• Required sensitivity / resolution
• Expected output format

Generate:
• Ranked instrument recommendations
• Scientific reasoning explanation
• Alternative techniques
• Capability limitations
• Confidence score

This layer demands domain-aware reasoning and explainability design.

B. Sample Preparation & Operational Intelligence
(Dynamic SOP Optimization Layer)

We move from static PDFs to adaptive workflows.
B1. Sample Preparation Intelligence

AI must dynamically tailor instructions based on:
• Sample composition
• Physical state (powder, liquid, thin film, biological, nano-material, etc.)
• Instrument sensitivity
• Research objective

System outputs must include:
• Particle size guidance
• Mounting protocols
• Solvent recommendations
• Concentration parameters
• Contamination control
• Storage and safety advisories
• Domain-specific warnings

B2. Dynamic SOP Optimization

Once equipment is selected, the system must:
• Adapt instrument parameters to research objective
• Suggest calibration logic
• Provide pre-run validation checklist
• Estimate experimental duration
• Highlight safety constraints
• Identify common failure points
• Optimize accuracy vs speed trade-offs

This module must combine LLM reasoning with deterministic validation logic.

C. AI-Assisted Result Interpretation
(Scientific Insight Layer)

The system must:
• Accept experiment metadata
• Interpret structured observations
• Flag anomalies
• Provide reasoning chains
• Suggest additional analysis
• Recommend complementary instruments
• Propose parameter refinement

Applicants must architect hallucination-control mechanisms and confidence scoring frameworks.
Explainability and scientific reliability are non-negotiable.

Deployment Roadmap
Phase 1 – Online AI Development
• RAG architecture
• Knowledge base structuring
• Prompt architecture design
• Reasoning validation
• Structured confidence scoring

Phase 2 – Offline AI Feasibility
• Model quantization
• Lightweight local inference
• CPU/GPU benchmarking
• Memory optimization
• Secure lab deployment architecture

The long-term objective is a fully offline AI assistant deployable inside laboratory ecosystems — secure, sovereign, and scalable.

Internship Duration
12–48 Weeks
(Duration aligned to scope and performance.)

Eligibility
• B.Tech / B.E. (CS, AI, Data Science, Electronics, Instrumentation, related fields)
• M.Sc. (AI, Computer Science, Data Science, Computational Sciences, related fields)

Higher qualifications are welcome but not mandatory.
Selection is based strictly on demonstrable AI system-building capability.

Compulsory Submission Requirements

Applicants must provide:
1. GitHub profile with relevant AI systems
2. Description of one AI system built
3. Technical Note (300–500 words):
“Design approach for an offline LLM system for scientific instrumentation.”

Applications without technical proof will not be evaluated.

Required Technical Depth
• LLM architecture understanding
• RAG implementation
• Prompt engineering
• Hybrid AI system design
• Python AI ecosystem (Transformers, LangChain, LlamaIndex, etc.)
• Edge model optimization

This is not a beginner internship.

We are looking for system architects in training.

Selection Process
• Technical screening
• AI project evaluation
• Technical note assessment
• Expert interview

Only candidates demonstrating strong AI implementation depth will be shortlisted.

National Impact

Selected interns will contribute to building an AI layer that can:
• Reduce experimental error
• Improve research efficiency
• Standardize instrument intelligence
• Democratize scientific access
• Lay foundation for AI-enabled research infrastructure

This is aligned with India’s long-term vision for digitally intelligent research systems.

Application Details
Forward the resume to spushpa@istem.co.in
The last date to apply for this position is 31.03.2026.

If you believe AI should move from content generation to infrastructure intelligence — this is your opportunity

The Micro Nano Characterization Facility (MNCF), Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science (IISc), Bengaluru, is a shared user facility that provides advanced materials characterization capabilities to researchers from academia, research institutions, and industry.

MNCF is inviting applications for the position of Facility Technologist in the field of Structural Characterization using X-ray Diffraction (XRD).

Essential Qualification: MSc / MTech / BTech in Physics, Chemistry, Materials Science or related Physical Sciences / Engineering disciplines.

Job Description: The selected candidate will play a critical role in the daily operation, maintenance, and data interpretation of X-ray diffraction (XRD) systems. The role involves supporting researchers in structural and crystallographic analysis of materials using powder
XRD, thin-film XRD, and high-resolution four-circle XRD techniques, ensuring instrument uptime, and maintaining rigorous documentation in compliance with international quality management standards.

The position is within a multi-user research facility environment, where the candidate will interact with researchers from academia and industry, assist them in planning experiments, ensure proper operation of the instruments, and maintain documentation in compliance with international quality management standards.

He/she should also train users on the proper use of the equipment, assist them during measurements, and maintain all operational records. The selected candidate will discharge any other duties assigned by the facility management from time to time. The position offers an opportunity to work closely with leading researchers at IISc and contribute to advanced materials characterisation studies across diverse fields, including
materials science, nanotechnology, electronics, and energy materials.

Roles and Responsibilities
 Instrument Operation: Perform routine and advanced measurements using X-ray diffraction systems, including powder X-ray diffraction for phase identification, thin- film θ–2θ measurements, grazing incidence X-ray diffraction (GIXRD), rocking curve measurements, reciprocal space mapping (RSM), pole-figure and texture analysis, residual stress measurements, X-ray reflectivity (XRR), and high-resolution four-circle
XRD measurements.

 Data Analysis: Assist users in crystallographic analysis, phase identification, lattice parameter determination, thin-film structural characterization, texture and orientation analysis, reciprocal space map interpretation, and Rietveld refinement of
powder diffraction data.

 Maintenance & Troubleshooting: Execute periodic calibration, preventive maintenance, and troubleshooting of XRD systems including X-ray sources, optics, detectors, goniometers, and sample stages, and coordinate hardware repairs when
required.

 User Facility Support: Train users and assist them during experiments. Guide users in planning diffraction measurements and ensure safe and proper operation of the instruments in a shared facility environment.

 Quality & Compliance: Maintain logbooks, Standard Operating Procedures (SOPs), and quality records in alignment with ISO management standards.

 Technical Reporting: Should be able to prepare detailed technical reports of the analysis.

Experience:
Prior hands-on experience operating X-ray diffraction (XRD) instruments is preferred. A solid understanding of crystallography, diffraction theory, and structural characterization of materials is desirable.

Experience in the following techniques will be an added advantage:
 Powder XRD analysis
 Thin-film XRD and grazing incidence XRD
 Reciprocal space mapping
 Texture and pole-figure measurements
 Rietveld refinement and diffraction data analysis

Candidates with demonstrated hands-on experience in independent operation, alignment, calibration, and troubleshooting of X-ray diffraction systems will be preferred. Applicants  should clearly indicate their hands-on experience with XRD instruments including system
alignment, calibration, data acquisition, and diffraction data analysis.

Experience working in a multi-user research facility, national laboratory, or shared instrumentation center will be an added advantage. Good communication skills, technical documentation ability, and user interaction skills are essential. Functional knowledge of ISO Management Standards (e.g., ISO 9001 or ISO/IEC 17025) is an added advantage.

 How to Apply: Please apply online using the following link Apply here on or before 24 March 2026.

Only shortlisted candidates will be contacted.

The Micro Nano Characterization facility (MNCF), Centre for Nanoscience and Engineering (CeNSE), Indian Institute of Science (IISc), Bengaluru, is inviting applications for the position of Facility technologist in the field of Surface Science & Chemical Characterization.

Essential Qualification: MSc / MTech / BTech in Physics, Chemistry, Materials Science or related Physical Sciences / Engineering disciplines.

Job Description: The selected candidate will play a critical role in the daily operation, maintenance, and data interpretation of X-ray photoelectron spectroscopy (XPS) systems. The role involves supporting researchers in chemical-state analysis, ensuring instrument uptime in an ultra-high vacuum (UHV) environment, and maintaining rigorous documentation in compliance with international quality management standards. He/she should also train/teach users of this equipment and maintain all records. Discharge any other duties assigned by the management from time to time.

Roles and Responsibilities
• Instrument Operation: Perform routine and advanced measurements, including survey scans, high-resolution core-level spectroscopy, and depth profiling.
• Data Analysis: Assist users in peak fitting, chemical state identification, and quantification using standard software (e.g., Avantage, CasaXPS).
• Maintenance & Troubleshooting: Execute periodic calibration, UHV maintenance (bake-outs, pump monitoring), and coordinate hardware repairs.
• Sample Management: Help and guide users on sample preparation techniques specifically for UHV environments to prevent system contamination.
• Quality & Compliance: Maintain logbooks, Standard Operating Procedures (SOPs), and quality records in alignment with ISO standards.
• Technical Reporting: Should be able to prepare detailed technical reports of the analysis

Experience: Prior Hands-on experience operating X-ray photoelectron spectroscopy (XPS) instruments is preferred. A solid understanding of Ultra-High Vacuum (UHV) systems and photoelectron physics is required. A basic understanding of material and device characterization is an added advantage. Basic proficiency in XPS data processing software (e.g., CasaXPS). Advanced expertise in spectral deconvolution and chemical shifting analysis. It is essential to have good communication skills. Proficiency in technical report writing and data documentation. Functional knowledge of ISO Management Standards (e.g., ISO 9001 or ISO/IEC 17025) is an added advantage.

How to Apply: Please apply online using the following link  Apply here on or before the 24th of March 2026

Applications are invited from motivated and eligible Indian Nationals for the position of Project Assistant to work on a funded project at the confluence of Engineering and Biology. The project focuses on the design and development of advanced Organ-on-Chip (OoC) and microfluidic devices. The selected candidate will work across the Centre for Nano Science and Engineering (CeNSE) and the Department of Developmental Biology and Genetics (DBG) at the Indian Institute of Science (IISc), under the joint supervision of Prof. Prosenjit Sen and Prof. Annapoorni Rangarajan.

Project Description:
The project involves building cutting-edge Organ-on-Chip platforms for disease modelling and drug screening. This interdisciplinary role offers the opportunity to design engineering solutions for complex biological problems, leveraging state-of-the-art nanofabrication and characterization facilities at CeNSE and biological expertise at DBG.

Position Details:

Role Title: Project Assistant – Microfluidic Device Design & Modelling
Nature of Appointment: Project-based / Contractual
Work Location: CeNSE & DBG, Indian Institute of Science (IISc), Bengaluru
Reporting To: Prof. Prosenjit Sen and Prof. Annapoorni Rangarajan

Key Responsibilities:

• Design and CAD modelling of complex microfluidic architectures and Organ-on-Chip devices.
• Perform computational simulations (CFD, stress analysis) to optimize device performance.
• Assist in the fabrication of microfluidic devices, specifically focusing on plastic-based manufacturing and prototyping.
• Collaborate with biologists to integrate physiological parameters into engineering designs.
• Maintain detailed documentation of design iterations, simulation results, and fabrication protocols.

Required Qualifications & Skills:

• Educational Background: B.E./B.Tech or M.E./M.Tech in Mechanical Engineering, Biomedical Engineering, Nanotechnology, or related fields.
• Essential Experience: Proficiency in SolidWorks or other CAD modelling software is mandatory.
• Technical Asset: Previous experience with COMSOL Multiphysics or ANSYS, specifically for microfluidic modelling (fluid flow, mass transport, etc.), is highly desirable.
• Preferred Skills: Knowledge of manufacturing techniques for plastic-based microfluidic devices (e.g., micromachining, injection molding, or 3D printing).

Remuneration
35-40k (consolidated) and based on the candidate’s qualification and experience.

How to Apply

Interested candidates should send their updated CV/Resume to the following email addresses: paladuguh@iisc.ac.in
Subject Line: Application for Project Assistant – Organ on Chip (Microfluidics)
Deadline for Application: 15th February 2025

A chief technology officer (CTO) position for the coordination and execution of activities in the Packaging and Systems facility (PASF) at CeNSE, IISc. Various programs are focusing on advanced packaging and integration technologies. In one such program, CeNSE is embarking on a path defining beyond CMOS technology. The program envisages to develop systems incorporation heterogeneous devices and technologies for applications in connectivity, IoT and Power. This includes integration of various base technologies such as compound semiconductors, sensors, MEMS, Photonics, and CMOS devices on a single functional substrate. Heterogeneous integration is the future of advanced systems. Quantum technologies is another program which is going to benefit from advanced packaging and integration. In addition to these upcoming programs, the facility is consistently developing technologies for MEMS sensor packaging.

The CTO is expected to be technically competent in one or more of the technologies mentioned above. The responsibilities include and are not limited to,

1. Day to day operation of the Packaging and Systems Facility (PASF).
2. Managing projects and training programs being executed under PASF.
3. Development of new technologies and process capabilities.
4. Identification and procurement of equipment.
5. Development of new training programs.
6. Interfacing and liaison with Government and private agencies.
7. Coordinate and follow up with potential partners and leads.
8. Hands on experience with the following technologies is a plus
   1. Thru substrate via and interposer technology
   2. Flip chip bonding
   3. Wafer scale packaging
   4. Vacuum packaging
   5. Hybrid bonding

Renumeration:

Up to 4 lakhs/month

Eligibility: 

1. A PhD/ME/MTech with a minimum of 10 years of relevant experience in technology program management.
2. Excellent oral and written communication in English.
3. Ability to plan and execute time-critical plans.
4. Financial planning is an added advantage.

The position is full-time located at CeNSE, Indian Institute of Science, Bangalore.

How to apply: Please apply online using the following link https://forms.gle/Xuc49YV1BKfYabo36

Last date for application: 16th January 2026

Job title : FT- Facility Technologist Systems Digital Design and Development
Reports to : SFT/ TM- Packaging Facility

Qualification – (BE/Diploma OR M. Tech 2-5 Years Experience)

Job purpose

The selected candidate will play a central role in architecting, implementing, and optimizing hardware-accelerated algorithms on FPGA platforms, along with seamless interfacing to analog and digital electronic systems developed in-house.

Roles and Responsibilites

• Design, implement, and optimize algorithms on FPGA platforms (Xilinx/Intel/others), including fixed-point and floating-point arithmetic
• Lead the architectural definition, RTL design (Verilog/VHDL), and implementation of FPGA-based systems from concept to production
• Develop detailed design specifications, block diagrams, and interface control documents
• Develop custom IP cores and data pipelines for real-time processing and control.
• Design and implement robust high-speed interfaces between FPGAs and external Analog PCBs, including ADCs, DACs, mixed-signal front-ends, and high-speed serial transceivers (SerDes, JESD204B, LVDS).
• Analyze and mitigate signal integrity, power integrity, and timing closure issues in high-speed digital and mixed-signal interfaces.
• Integrate and customize RISC-V soft-core processors within the FPGA, including bus interfaces (AXI, APB, AHB), memory controllers (DDR, BRAM), custom instruction development, and hardware-software co-design.
• Develop comprehensive verification strategies, test plans, and test benches using simulation tools (e.g., QuestaSim, VCS).
• Perform rigorous functional verification, formal verification, and hardware-in-the-loop (HIL) testing.
• Utilize on-chip debugging tools (e.g., Xilinx ILA, Intel SignalTap) for efficient hardware validation and troubleshooting.
• Assist in translating high-level algorithmic descriptions (e.g., in MATLAB, Python) into efficient HDL implementations.

Skills and Experience

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics and Communication Engineering, Computer Engineering, or a related field.
• 2-5 Years experience in the below areas in reputed industry
• Hands-on experience in FPGA design, development, and verification.
• Expert proficiency in RTL design using Verilog and/or VHDL.
• Extensive experience with major FPGA vendor toolchains (e.g., Xilinx Vivado, Intel Quartus Prime) including synthesis, place & route, and timing closure.
• Experience in designing and debugging high-speed interfaces with Analog PCBs (ADCs, DACs, SerDes, LVDS, JESD204B).
  JD For Packaging and Systems Facility-CeNSE IISc
• Experience with soft-core processor integration, specifically RISC-V, including familiarity with AXI/APB/AHB bus protocols and memory controllers (DDRx).
• Solid understanding of digital signal processing (DSP) concepts and their implementation in FPGAs.
• Proficiency with version control systems (e.g., Git).
• Experience with SystemVerilog and UVM methodology for advanced verification.
• Familiarity with embedded Linux on FPGA SoCs (e.g., Zynq, Arria V/10, Versal).
• Scripting skills (Python, Tcl) for automation of design and verification flows.
• Experience with high-speed communication protocols (e.g., PCIe, Ethernet).

Good communication skills and team work is a must.
Interested candidates to send their detailed resume with current CTC to krishnapr@iisc.ac.in

Job title:  SFT-Systems Facility-CeNSE-IISc
Reports to:  TM- Systems Facility

Qualification – (BE OR M. Tech 6-10 Years Experience)

Job purpose
To Lead a Team for Designing Hardware, Firmware for Projects and Academic Users for Design Services at PASF (Packaging and Systems Facility) CeNSE- IISc.

Duties and responsibilities

1. To Design Hardware, Firmware, Develop Algorithms and Support Academic Projects.
2. Interact & Guide other Design /FT Engineers to complete Activities on Time
3. Provide Guidance for PCB Design and Layout to FT/Engineers.
4. Assist Interns to Complete Protos or testing or take up part of Project work.
5. Provide Modules/Systems/Prototypes as per User or Project Requirements with focus on Creativity, Innovation and Cost Optimisation.
6. Participate in Exhibitions & Open Day Events as required by CeNSE-IISC.
7. Report to Technology Manager and Track FOM and timelines of the progress.
8. Upkeep of Lab Equipments and Inventory.
9. Ensure that Design Services Time is Utilised fully and upkeep the data log.
10. Visit or Interact with Customers as required for Project Discussions and other Project related Activities like Field Deployment or Deliverables as per Project Requirements.

Qualifications, Skills & Experience

1. B.E/ME/M Tech in Electronics/ Instrumentation/ Electronics & Communications experience with at Least 6-10 Years’ in Reputed Industry
2. Understanding System Design, Architecture and complete Solutions.
3. Usage of Standard tools for Design tools like AMS & Altium or Suitable Tools such as Matlab, Analog and Digital Circuit Simulation Tools like Spice.
4. Arm or Microcontroller Tools Useage on Various Platforms such as STM/Arduino/Raspberry PI etc etc
5. Programming Skills C, C++, Python, Java.
6. Strong attention to detail, persistence, follow through and ability to work with minimal supervision are essential.
7. High energy, self motivated with strong communication skills and personal work ethics, a sense of ownership as well as ability to work as a team.
8. Good in Communication and Documentation.
9. Lead the Team to achieve the goals and objectives of the Group
10. ISO9001, 45001 and other documentation procedures knowledge and participate in Internal and external audits.

Resumes to be shared with krishnapr@iisc.ac.in

Job title : Facility Technologist (FT)-Systems Facility
Reports to :  SFT- Systems Facility

Qualification – (BE/Diploma OR M. Tech with 2-8 Years Experience)

Job purpose
To Design and Develop new Hardware/Firmware as per Technical specifications or requirement of the Project.

Roles and Responsibilites

• To design and develop Hardware or Firmware.
• Timely execution of projects and participate in reviews and meetings with team.
• Keep up to date documents pertaining to Standard Operating Procedures, design and development files.
• Ensure that safety procedures are followed, and SOP is prepared for the activities carried out .
• To support projects by giving inputs at relevant times and by helping the SFT/TM on technical aspects
• Prepare training materials/conduct training for Interns and New Joinees
• Update with new Technology and support Students or users as required in the relevant areas
• Familiar and upgrade the tools and skill sets as required
• Identify training requirements with SFT/TM and ensure training helps in executing projects
• Bring to notice issues faced both Technical and Operational in review meetings and discuss with SFT/ TM to resolve the same

Skills and Experience

• Programming Skills C, C++, Python, Java.
• Hardware Design and Tools such as PCB Layout, Analysis.
• Analog and Digital Design with Simulation skills and Analysis.
• Testing and Trouble shooting.
• Strong attention to detail, persistence, follow through and ability to work with minimal supervision are essential.
• High energy, self motivated with strong communication skills and personal work ethics, a sense of ownership as well as ability to work as a team.
• Good in Communication and Documentation

Resume to be sent to krishnapr@iisc.ac.in

Looking for post-doc, project associates and project assistant staff to develop gallium oxide power devices. Under a mission-mode MeitY project, our goal is to develop the full technology of heterojunction gallium oxide power devices, including fabrication, characterisation, design, materials, and stability. The team hired in this project will interact with Prof. Sushobhan Avasthi and Prof. Digbijoy Nath.

Qualification: Must have experience in one of following: materials, device physics, fabrication, characterization or testing. Designation will depend on degree (MSc/BTech/Masters/PhD).

Salary: As per DST norms.

Tenure: 2 month probation. After that position will be on 6 month contracts, expendable to 3 years.

Interested people can apply at https://forms.gle/jmkEizB6M6yWdJ648

Job Title:
Software Developer – Python/C++ for on-chip photonic device design

Job Summary:
We are seeking a motivated and talented Software Developer with expertise in Python and/or C++ scripting to join our team. The ideal candidate will work on developing, and maintaining designs for on-chip photonics-related applications.

Key Responsibilities:
• Develop, test, and maintain high-quality software scripts using Python and/or C++.
• Collaborate with cross-functional teams, to understand and implement requirements.
• Document software designs, test cases, command usage, and user guides.

Required Skills and Qualifications:
• Proficiency in Python and/or C++ programming with a focus on clean and efficient coding practices.
• Strong analytical and problem-solving skills with a keen attention to detail.
• Knowledge of software development tools such as Git, debugging tools, and IDEs.
• Background in physics, electrical engineering, or related fields is a plus.
• Experience in writing and debugging code that utilizes SCPI commands for instrument control is a plus

Educational Qualifications:
• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, Physics, or a related field. Candidates with equivalent practical experience are also encouraged to apply.

Soft Skills:
• Excellent communication skills to interact with team members.
• Ability to work independently and collaboratively in a team environment.
• Strong organizational and time-management skills.

Experience Level:
• 2+ years of experience in software development (Python and/or C++) with exposure to SCPI-based programming.

Salary: As per DST norms

Location: Centre for Nano Science and Engineering, IISc

Application Process:  Click here to apply
Interested candidates are encouraged to submit the following:
• Updated resume/CV.

Role & Responsibility
• Fabrication of van der Waals heterostructure.
• Electronic transport measurement at cryogenic temperature.

Qualification: Candidate must have MSc degree in Physics

Tenure and Compensation: 1 year (extendable up to 3) and salary as per DST norms.

Send resume to kchandan@iisc.ac.in subject as “Application for JRF position”

Immediate opening for Postdoctoral fellow position is available to work on Biosensors. The duration of the position can be upto 2 years, subject to satisfactory performance. Candidate should be willing to design the experiments based on project requirement, work in a multidisciplinary group interacting with Biologists, Chemists, Engineers and Clinicians. Candidate should be familiar in handling biological samples such as blood and urine. Interested candidates can send their detailed CV to navakant@iisc.ac.in with a copy to navakant@gmail.com. The subject line of the email should be “Biosensors Postdoc Position”.

Desired qualifications: PhD in Biochemistry, Chemistry, Biotechnology with previous degree in Biochemistry, Chemistry, Biotechnology.

Skill sets required: Good understanding of Protein Chemistry, Enzymology, Electrochemistry, Protein Glycation, Mass spectroscopy, UV Spectroscopy, Cell culture.