Thesis Title: “Development of recessed-gate normally-off AlxGa1-xN/GaN HEMTs for power applications” 

Name of the Student: Mr. SHANTVEER KANTA

SR No :  05-16-00-10-12-18-1-15901

Degree Registered: Ph.D. Engineering  

Advisor: Prof. Srinivasan Raghavan, Prof. Navakanta Bhat, CeNSE  

Date: 22nd December 2025 (Monday), Time: 2 PM 

Venue: Seminar Hall, CeNSE :https://shorturl.at/I7QRl

Abstract:

The push for higher efficiency and power density in power electronics has accelerated the development 
of AlGaN/GaN high electron mobility transistors (HEMTs). The formation of a two-dimensional electron 
gas (2DEG) at the AlGaN/GaN heterointerface, combined with the wide bandgap of GaN, offers key 
advantages such as high on-state current and high breakdown voltage - making these devices highly 
attractive for high-voltage switching applications. However, their native normally-on behaviour requires 
a constant negative gate bias to keep the device in the off-state, which increases circuit complexity and 
raises reliability concerns. In contrast, normally-off (enhancement-mode) operation is preferred for safe 
and fail-secure switching, along with the benefit of simplified gate drive circuitry. Despite significant 
progress, achieving a high and reliable threshold voltage (Vth) in normally-off AlGaN/GaN HEMTs remains a 
critical challenge.

This thesis focuses on the design, fabrication, and characterization of recessed-gate AlGaN/GaN MIS-HEMTs 
to enable reliable normally-off operation. The work begins with a detailed analysis of Vth requirements, 
highlighting the need for Vth ≥ 3 V to prevent parasitic turn-on. One effective way to achieve high Vth 
is by utilizing negative trapped charges within the insulator. In this context, the presence of negative 
oxide traps in atomic layer deposited (ALD) Al2O3 is experimentally validated as an effective mechanism 
to shift the threshold voltage positively and achieve enhancement-mode operation.

Subsequently, the fabrication of high-Vth MIS-HEMTs is demonstrated using a recessed-gate architecture 
and low-damage digital etching. Gate programmability and retention behaviour are studied to assess Vth 
stability over time. A Vth of 6 V was achieved after the application of an 11 V gate program voltage, 
with the device exhibiting good retention characteristics. Dynamic measurements are then used to 
investigate Vth hysteresis and its effect on switching delays under various gate voltage conditions, 
confirming minimal impact on turn-off behaviour.

The next part addresses interface engineering through ex-situ plasma pretreatments to enhance the 
Al2O3/GaN interface. Treatments such as N2 and NH3 + N2 plasmas are found to significantly improve drain 
current, field-effect mobility, and reduce interface trap density, whereas N2O treatment leads to performance 
degradation due to GaN surface reoxidation. Devices subjected to N2 plasma pretreatment exhibited enhancements 
of 123% in the maximum drain-current and 107% in the maximum field-effect mobility, alongside a 56% reduction 
in threshold voltage hysteresis compared to untreated devices.  Frequency dependent C-V analyses confirmed a 
significant reduction in interface trap density for both N2 and NH3+N2 treatments, with the latter achieving 
a 46.8% reduction in interface traps compared to untreated devices.

To further improve Vth stability and suppress gate leakage, a bilayer dielectric stack combining PECVD SiO2 
and ALD Al2O3 is implemented. This bilayer approach demonstrates enhanced retention, lower Vth shift under 
bias stress, and a higher gate breakdown voltage, making it a robust solution for high-voltage GaN power devices.

Overall, this thesis contributes critical insights into threshold voltage engineering, interface optimization, 
and dielectric reliability - key enablers for advancing normally-off AlGaN/GaN MIS-HEMTs in next-generation power electronics.