Ph.D. Electrical Engineering, 2006, University of Washington, Seattle, USA.
B. Tech (Hons.) in ECE, 1997, Indian Institute of Technology, Kharagpur, India
Experience:
Assistant Professor, Indian Institute of Science, Bangalore, India, May 2010- current.
Staff Engineer, Qualcomm Inc, Austin TX, USA, April 2007 – March 2010.
Staff Scientist, Intel Corp., Hillsboro OR, USA, June 1999 – March 2007.
Patents
G. Banerjee, M. Behera, K. Barnett, Methods and apparatus for providing a built-in self test, U.S. Patent No. US 8589750 B2, Granted Nov. 19, 2013.
G. Banerjee, M. Behera, A signal generator for a built-in self test, U.S. Patent Publication No. US20110273197 A1, Filed May 7, 2011, Published Nov 10, 2011.
G. Banerjee, S. R. Mooney, Passive impedance equalization of high speed serial links, U. K. Patent No. GB2449799, Granted March 9, 2011.
G. Banerjee and K. Soumyanath, Reference impedance apparatus, systems, and methods, U.S. Patent # 6,998,931, Assignee: Intel Corp.
G. Banerjee and K. Soumyanath, Strained-silicon voltage controlled oscillator, Taiwanese patent # I295124, Assignee: Intel Corp.
G. Banerjee and K. Soumyanath, Strained-silicon voltage controlled oscillator, U.S. Patent # 7,049,898, Assignee: Intel Corp.
G. Banerjee and R. Mooney, Passive impedance equalization of high speed serial links, Taiwanese patent pending (App# 200737714), Assignee: Intel Corp.