Intrinsic limits of channel transport hysteresis in graphene-SiO2 interface and its dependence on graphene defect density

Hysteresis in channel conductance is commonly observed on graphene field effect transistors. Although consistent and repeatable hysteresis could possibly be attractive for memory based applications, it is detrimental to the deployment of graphene in high speed electronic switches. While the origin of such hysteresis has been variously attributed to graphene-insulator interface traps, adsorbed molecules and bulk charges in the dielectric, its dependence on the quality of the graphene has been largely unexplored. Since, CVD is the most promising synthesis route for large area graphene and defects in such a growth process are inevitable, it is important to understand the influence of the quality of graphene on hysteresis. Here we demonstrate, for the first time, the effect of graphene growth defect density on device hysteresis. By intentionally tailoring the defect densities in the growth phase, we demonstrate a linear correlation between the film defect density and conductance hysteresis. The trap charge density calculated from the observed hysteresis in the electrical transfer characteristics was found to both follow the same qualitative trend, and give reasonable quantitative agreement with the defect density as extracted from Raman spectroscopy. Most importantly, by extrapolation from the observed behavior, we identify the intrinsic limits of hysteresis in graphene-SiO₂ system, demonstrating that the defects in graphene contribute to traps over and above the baseline set by the SiO₂ surface trap charge density.