| Title | Underlap Optimization in HFinFET in Presence of Interface Traps |
| Publication Type | Journal Article |
| Year of Publication | 2011 |
| Authors | Majumdar, K, Konjady, RS, Suryaprakash, RT, Bhat, N |
| Journal | IEEE Transactions on Nanotechnology |
| Volume | 10 |
| Pagination | 1249-1253 |
| Date Published | Nov |
| ISSN | 1536-125X |
| Keywords | 3D device simulation, Coupled poisson-schrodinger equations, device quality degradation, FinFET, FinFETs, HEMT, HFinFET, hybrid transistor, III-V transistor, Interface states, interface traps, ITRS 2009 performance projection, logic gates, MOSFET, MOSFET circuits, ON performance degradation, ON-OFF ratio, optimisation, Performance evaluation, Poisson equations, silicon MOSFET data, Transistors, ultrashort channel n-type device, underlap optimization |
| Abstract | In this work, using 3-D device simulation, we perform an extensive gate to source/drain underlap optimization for the recently proposed hybrid transistor, HFinFET, to show that the underlap lengths can be suitably tuned to improve the ON-OFF ratio as well as the subthreshold characteristics in an ultrashort channel n-type device without significant ON performance degradation. We also show that the underlap knob can be tuned to mitigate the device quality degradation in presence of interface traps. The obtained results are shown to be promising when compared against ITRS 2009 performance projections, as well as published state of the art planar and nonplanar Silicon MOSFET data of comparable gate lengths using standard benchmarking techniques. |
| DOI | 10.1109/TNANO.2011.2119401 |
