| Title | A 0.1 #x2013;3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS |
| Publication Type | Journal Article |
| Year of Publication | 2016 |
| Authors | Raja, I, Banerjee, G, Zeidan, MA, Abraham, JA |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 24 |
| Pagination | 1975-1983 |
| Date Published | May |
| ISSN | 1063-8210 |
| Keywords | 50% duty cycle, Bandwidth, Clocks, CMOS, CMOS integrated circuits, CMOS technology, correction circuit, correction loop, detector circuits, duty cycle, duty-cycle correction (DCC), duty-cycle correction technique, duty-cycle measurements, frequency 100 MHz to 3.5 GHz, frequency domain data, frequency domain measurements, frequency measurement, Harmonic analysis, pulsewidth modification cell, rise-fall times, rise/fall time measurements, rise/fall time measurements., size 0.13 mum, time domain measurements, Time-frequency analysis, Voltage control |
| Abstract | A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz-3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An alternative method of making time domain measurements such as duty cycle and rise/fall times from the frequency domain data is introduced. The data are obtained from the equipment that has significantly lower bandwidth than required for measurements in the time domain. An algorithm for the same has been developed and experimentally verified. The correction circuit is implemented in a 0.13-μm CMOS technology and occupies an area of 0.011 mm2. It corrects to a residual error of less than 1%. The extent of correction is limited by the technology at higher frequencies. |
| DOI | 10.1109/TVLSI.2015.2478804 |
