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Analytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes

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TitleAnalytical modeling of CMOS circuit delay distribution due to concurrent variations in multiple processes
Publication TypeJournal Article
Year of Publication2006
AuthorsHarish, BP, Bhat, N, Patil, MB
JournalSolid State Electronics
Volume50
Pagination1252-1260
Research Area: 
Electronics