Title | SEU reliability improvement due to source-side charge collection in the deep-submicron SRAM cell |
Publication Type | Journal Article |
Year of Publication | 2003 |
Authors | Saxena, PK, Bhat, N |
Journal | IEEE Transactions on Device and Materials Reliability |
Volume | 3 |
Pagination | 14-17 |
Date Published | Mar |
ISSN | 1530-4388 |
Keywords | 0.5 to 0.09 micron, Circuit simulation, CMOS technology, critical charge, deep-submicron SRAM cell, Discrete event simulation, drain node, Energy exchange, Feedback, feedback time, integrated circuit reliability, Leakage current, linear energy transfer, MOS devices, MOSFETs, radiation effects, radiation-induced charge, Random access memory, Reliability engineering, SEU reliability, single event upset, source node, source-side charge collection, SRAM chips, technology scaling, two-dimensional device simulation, ULSI |
Abstract | The effect of technology scaling (0.5-0.09 μm) on single event upset (SEU) phenomena is investigated using full two-dimensional device simulation. The SEU reliability parameters, such as critical charge (Qcrit), feedback time (Tfd) and linear energy transfer (LET), are estimated. For Lg |
DOI | 10.1109/TDMR.2003.808979 |