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SEU reliability improvement due to source-side charge collection in the deep-submicron SRAM cell

TitleSEU reliability improvement due to source-side charge collection in the deep-submicron SRAM cell
Publication TypeJournal Article
Year of Publication2003
AuthorsSaxena, PK, Bhat, N
JournalIEEE Transactions on Device and Materials Reliability
Volume3
Pagination14-17
Date PublishedMar
ISSN1530-4388
Keywords0.5 to 0.09 micron, Circuit simulation, CMOS technology, critical charge, deep-submicron SRAM cell, Discrete event simulation, drain node, Energy exchange, Feedback, feedback time, integrated circuit reliability, Leakage current, linear energy transfer, MOS devices, MOSFETs, radiation effects, radiation-induced charge, Random access memory, Reliability engineering, SEU reliability, single event upset, source node, source-side charge collection, SRAM chips, technology scaling, two-dimensional device simulation, ULSI
Abstract

The effect of technology scaling (0.5-0.09 μm) on single event upset (SEU) phenomena is investigated using full two-dimensional device simulation. The SEU reliability parameters, such as critical charge (Qcrit), feedback time (Tfd) and linear energy transfer (LET), are estimated. For Lg

DOI10.1109/TDMR.2003.808979