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Publications

Found 808 results
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W. Bogaerts, Selvaraja, S. K. , Dumon, P. , Brouckaert, J. , De Vos, K. , Van Thourhout, D. , and Baets, R. , “Silicon-on-Insulator Spectral Filters Fabricated with CMOS Technology”, IEEE Journal of Selected Topics in Quantum Electronics, vol. 16, pp. 33–44, 2010.
W. Bogaerts and Selvaraja, S. K. , “Compact Single-mode Silicon Hybrid Rib/Strip Waveguide with Adiabatic Bends”, IEEE Photonics Journal, vol. 3, pp. 422–232, 2011.
W. Bogaerts, De Heyn, P. , Van Vaerenbergh, T. , De Vos, K. , Selvaraja, S. K. , Claes, T. , Dumon, P. , Bienstman, P. , Van Thourhout, D. , and Baets, R. , “Silicon Microring Resonators”, Lasers and Photonics Review, vol. 6, pp. 47–73, 2012.
T. Biswas, Ravindra, P. , Athresh, E. , Ranjan, R. , Avasthi, S. , and Jain, M. , “Optical Properties of Zn2Mo3O8: Combination of Theoretical and Experimental Study”, The Journal of Physical Chemistry C, vol. 121, pp. 24766–24773, 2017.
K. S. Bhosale, Zope, A. A. , Pillai, G. , and Li, S. - S. , “Tiny-Gap Titanium-Nitride-Composite MEMS Resonator Designs With High Power Handling Capability”, Journal of Microelectromechanical Systems, 2023.
S. Bhattacharjee, Ganapathi, K. Lakshmi, Mohan, S. , and Bhat, N. , “A sub-thermionic MoS2 FET with tunable transport”, Applied Physics Letters, vol. 111, p. 163501, 2017.
S. Bhattacharjee, Ganapathi, K. L. , Nath, D. N. , and Bhat, N. , “Surface State Engineering of Metal/MoS2 Contacts Using Sulfur Treatment for Reduced Contact Resistance and Variability”, IEEE Transactions on Electron Devices, vol. 63, pp. 2556-2562, 2016.
S. Bhattacharjee, Ganapathi, K. L. , Nath, D. N. , and Bhat, N. , “Intrinsic Limit for Contact Resistance in Exfoliated Multilayered MoS2 FET”, IEEE Electron Device Letters, vol. 37, pp. 119-122, 2016.
S. Bhattacharjee, Ganapathi, K. L. , Mohan, S. , and Bhat, N. , “Interface Engineering of High-k Dielectrics and Metal Contacts for High Performance Top-Gated MoS2 FETs”, ECS Transactions, vol. 80, pp. 101–107, 2017.
S. Bhattacharjee, Ganapathi, K. Lakshmi, Nath, D. N. , and Bhat, N. , “Sulfur treatment for schottky barrier reduction in metal/MoS2 contacts: A new proposal for contact engineering on TMDs”, arXiv preprint arXiv:1508.03795, 2015.
S. Bhattacharjee, Ganapathi, K. Lakshmi, Nath, D. N. , and Bhat, N. , “Intrinsic limit for contact resistance in exfoliated multilayered MoS 2 FET”, IEEE Electron Device Letters, vol. 37, pp. 119–122, 2016.
S. Bhattacharjee, Vatsyayan, R. , Ganapathi, K. Lakshmi, Ravindra, P. , Mohan, S. , and Bhat, N. , “Hole Injection and Rectifying Heterojunction Photodiodes through Vacancy Engineering in MoS2”, Advanced Electronic Materials, p. 1800863, 2019.
S. Bhattacharjee, Ganapathi, K. Lakshmi, Sharma, D. Ganesh, Sharma, A. , Mohan, S. , and Bhat, N. , “Adaptive Transport in High Performance (I on), Steep Sub-Threshold Slope (SS< 60 mV/dec) MoS 2 Transistors”, IEEE Transactions on Nanotechnology, vol. 18, pp. 1071–1078, 2019.
S. Bhattacharjee, Ganapathi, K. Lakshmi, Chandrasekar, H. , Paul, T. , Mohan, S. , Ghosh, A. , Raghavan, S. , and Bhat, N. , “Nitride Dielectric Environments to Suppress Surface Optical Phonon Dominated Scattering in High-Performance Multilayer MoS2 FETs”, Advanced Electronic Materials, vol. 3, 2017.
S. Bhattacharjee, Ganapathi, K. Lakshmi, Nath, D. N. , and Bhat, N. , “Surface state engineering of metal/MoS 2 contacts using sulfur treatment for reduced contact resistance and variability”, IEEE Transactions on Electron Devices, vol. 63, pp. 2556–2562, 2016.
N. Bhat, “MEMS for RF Applications”, IETE Technical Review, vol. 21, 2004.
N. Bhat and Thakur, C. S. , “Analog CMOS Performance Degradation due to Edge Direct Tunneling (EDT) Current in sub-100nm Technology”, Journal of Semiconductor Technology and Science, 2003.
N. Bhat, “Nanoelectronics Era: Novel Device Technologies Enabling Systems on Chip”, Journal of the Indian Institute of Science, vol. 87, pp. 61–74, 2007.
S. G. Bhat and Kumar, P. S. A. , “Room temperature electrical spin injection into GaAs by an oxide spin injector”, Scientific Reports., vol. 4, 2014.
N. Bhat and Saraswat, K. C. , “Characterization of border trap generation in rapid thermally annealed oxides deposited using silane chemistry”, Journal of Applied Physics, p. 2722, 1998.
M. K Bhat, Mandal, S. , Pathak, S. , G Saravanan, S. , Sridhar, C. , Badnikar, S. L. , Vyas, H. P. , Muralidharan, R. , Jain, M. K. , and Subrahmanyam, A. , “Gate recess structure engineering using silicon-nitride-assisted process for increased breakdown voltage in pseudomorphic HEMTs”, Semicond. Sci. Technol, vol. 27, 2012.
N. Bhat and Nandy, S. K. , “Special Purpose Architecture for Accelerating Bitmap DRC”, in Design Automation, 1989. 26th Conference on, 1989, pp. 674-677.
N. Bhat, Cao, M. , and Saraswat, K. C. , “Bias temperature instability in hydrogenated thin-film transistors”, IEEE Transactions on Electron Devices, p. 1102, 1997.
N. Bhat, Wang, A. , and Saraswat, K. C. , “Rapid thermal anneal of gate oxides for low thermal budget TFTs”, IEEE Transactions on Electron Devices, p. 63, 1999.
N. Bhat, Apte, P. P. , and Saraswat, K. C. , “Charge trap generation in LPCVD oxides under high field stressing”, IEEE Transactions on Electron Devices, p. 554, 1996.

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