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Publications

Found 363 results
Author Title Type [ Year(Asc)]
Filters: First Letter Of Last Name is B  [Clear All Filters]
2003
H. C. Srinivasaiah and Bhat, N. , “Monte Carlo Analysis of the Implant Dose Sensitivity in 0.1 nm NMOSFET”, Solid-State Electronics, vol. 47/8, pp. 1379–1383, 2003.
K. Maitra and Bhat, N. , “Polyreoxidation process step for suppressing edge direct tunneling through ultrathin gate oxides in NMOSFETs”, Solid-State Electronics, vol. 47, pp. 15–17, 2003.
P. K. Saxena and Bhat, N. , “Process technique for SEU reliability improvement of deep sub-micron SRAM cell”, Solid-State Electronics, vol. 47, pp. 661–664, 2003.
P. K. Saxena and Bhat, N. , “SEU Reliability Improvement Due to Source-Side Charge Collection in the Deep-Submicron SRAM Cell”, IEEE Transactions on Device and Material Reliability, pp. 14–17, 2003.
P. K. Saxena and Bhat, N. , “SEU reliability improvement due to source-side charge collection in the deep-submicron SRAM cell”, IEEE Transactions on Device and Materials Reliability, vol. 3, pp. 14-17, 2003.
M. P. Singh, Thakur, C. S. , Shalini, K. , Bhat, N. , and Shivashankar, S. A. , “Structural and Electrical Characterization of Erbium Oxide Films Grown on Si(100) by Low-pressure Metalorganic Chemical Vapour Deposition”, Applied Physics Letters, 2003.
S. Patil, Venkatesh, C. , Bhat, N. , and Pratap, R. , “Voltage Controlled Oscillator using Tunable MEMS Resonator”, International Journal of Computational Engineering Science, vol. 4, 2003.
1999
N. Bhat, Wang, A. , and Saraswat, K. C. , “Rapid thermal anneal of gate oxides for low thermal budget TFTs”, IEEE Transactions on Electron Devices, p. 63, 1999.
1998
N. Bhat and Saraswat, K. C. , “Characterization of border trap generation in rapid thermally annealed oxides deposited using silane chemistry”, Journal of Applied Physics, p. 2722, 1998.
1997
N. Bhat, Cao, M. , and Saraswat, K. C. , “Bias temperature instability in hydrogenated thin-film transistors”, IEEE Transactions on Electron Devices, p. 1102, 1997.
1996
N. Bhat, Apte, P. P. , and Saraswat, K. C. , “Charge trap generation in LPCVD oxides under high field stressing”, IEEE Transactions on Electron Devices, p. 554, 1996.
1992
N. Bhat and Vasi, J. , “Interface-state generation under radiation and high field stressing in reoxidized nitrided oxide MOS capacitors”, IEEE Transactions on Nuclear Science, p. 2230, 1992.
1989
N. Bhat and Nandy, S. K. , “Special Purpose Architecture for Accelerating Bitmap DRC”, in Design Automation, 1989. 26th Conference on, 1989, pp. 674-677.

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